AN EXPERIMENTAL 1 MBIT DRAM BASED ON HIGH S/N DESIGN

被引：7

作者：

HORI, R

ITOH, K

ETOH, J

ASAI, S

HASHIMOTO, N

YAGI, K

SUNAMI, H

机构：

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1984年 / 19卷 / 05期

关键词：

D O I：

10.1109/JSSC.1984.1052201

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

引用

页码：634 / 640

页数：7

共 14 条

[1]

EATON S, 1981, FEB ISSCC, P84

[2]

ITOH K, 1983, IEE PROC-I, V130, P127, DOI 10.1049/ip-i-1.1983.0024

[3]

ITOH K, 1984, FEB IEEE INT SOL STA, P282

[4]

ITOH K, 1980, FEB IEEE ISSCC, P228

[5]

KOYANAGI M, 1979, 10TH P C SOL STAT S, V18, P35

[6]

MANO T, 1983, FEB ISSCC, P234

[7]

MORIE T, 1982, SEP JAP SOC APPL PHY

[8] 1 MU-M MOSFET VLSI TECHNOLOGY .4. HOT-ELECTRON DESIGN CONSTRAINTS [J].

NING, TH ;

COOK, PW ;

DENNARD, RH ;

OSBURN, CM ;

SCHUSTER, SE ;

YU, HN .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1979, 14 (02) :268-275

[9] DESIGN AND CHARACTERISTICS OF THE LIGHTLY DOPED DRAIN-SOURCE (LDD) INSULATED GATE FIELD-EFFECT TRANSISTOR [J].

OGURA, S ;

TSANG, PJ ;

WALKER, WW ;

CRITCHLOW, DL ;

SHEPARD, JF .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 1980, 27 (08) :1359-1367

[10]

SUNAMI H, 1982, DEC IEDM, P806

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