N-WELL AND P-WELL OPTIMIZATION FOR HIGH-SPEED N-EPITAXY CMOS CIRCUITS

被引:5
作者
SCHWABE, U
HERBST, H
JACOBS, EP
TAKACS, D
机构
关键词
D O I
10.1109/T-ED.1983.21295
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
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页码:1339 / 1344
页数:6
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[2]   ELECTRICAL MEASUREMENT OF FEATURE SIZES IN MOS SI2-GATE VLSI TECHNOLOGY [J].
TAKACS, D ;
MULLER, W ;
SCHWABE, U .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1980, 27 (08) :1368-1373
[3]  
Takacs D., 1982, International Electron Devices Meeting. Technical Digest, P458