PERFORMANCE POTENTIAL OF SILICON BIPOLAR-TRANSISTORS

The performance potential of silicon bipolar transistors is investigated by device simulation. Using a one-dimensional drift-diffusion equation solver, the SPICE parameters of self-aligned transistors are extracted from doping profiles and device geometries. These parameters are used to predict the CML gate delay for different doping profiles. The validity of this extraction procedure is verified by comparison with experimental data. For a double-diffusion type doping profile with a pinch resistance of 15 k-OMEGA/square, a transit frequency of 56 GHz and a CML gate delay of approximately 15 ps are achievable. With a doping profile including a low-doped emitter region and a high base doping concentration, significant improvements are found: A transit frequency of 81.6 GHz and a pinch resistance of 10 k-OMEGA/square enable CML gate delay times below 10 ps.