A 336-NEURON, 28K-SYNAPSE, SELF-LEARNING NEURAL NETWORK CHIP WITH BRANCH-NEURON-UNIT ARCHITECTURE

被引：24

作者：

ARIMA, Y

MASHIKO, K

OKADA, K

YAMADA, T

MAEDA, A

NOTANI, H

KONDOH, H

KAYANO, S

机构：

[1] LSI Laboratory, Mitsubishi Electric Corporation, Itami-shi, Hyogo, 664

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1991年 / 26卷 / 11期

关键词：

D O I：

10.1109/4.98984

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper describes a self-learning neural network chip based on the branch-neuron-unit (BNU) architecture, which expands the scale of neural network by interconnecting multiple chips without reducing performance. The chip integrates 336 neurons and 28 224 synapses with a 1.0-mu-m double-poly-Si double-metal CMOS technology. The operation speed is higher than 1 x 10(12) connections per second per chip. It is estimated that the network scale can be expanded to several hundred chips. In the case of 200 chips interconnections, the network will consist of 3360 neurons and 5 644 800 synapses.

引用

页码：1637 / 1644

页数：8

共 11 条

[1]

ACKLEY DH, 1985, COGNITIVE SCI, V9, P147

[2]

Alspector J., 1987, Advanced Research in VLSI. Proceedings of the 1987 Stanford Conference, P313

[3] LEARNING PATTERNS AND PATTERN SEQUENCES BY SELF-ORGANIZING NETS OF THRESHOLD ELEMENTS [J].