BUILT-IN SELF TESTING OF EMBEDDED MEMORIES

A built-in self-test (BIST) method for testing embedded memories is presented. Two algorithms are proposed for self-testing of embedded RAMs, both of which can detect a large variety of stuck-at and non-stuck-at faults. The hardware implementation of the methods requires a hardware test-pattern generator which produces address, data, and read/write inputs. The output responses of the memory can be compressed by using a parallel input signature analyzer, or they can be compared with expected responses by an output comparator. The layout of memories has been considered in the design of additional BIST circuitry. The two schemes proposed are evaluated on the basis of area overhead, performance degradation, fault coverage, test application time, and testing of self-test circuitry. The BIST overhead is very low and test time is quite short. Six devices using one of the test schemes have been manufactured and are in the field.