DRAIN-INDUCED BARRIER-LOWERING ANALYSIS IN VLSI MOSFET DEVICES USING TWO-DIMENSIONAL NUMERICAL SIMULATIONS

被引:56
作者
CHAMBERLAIN, SG
RAMANAN, S
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D O I
10.1109/T-ED.1986.22737
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
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页码:1745 / 1753
页数:9
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