SEMIEMPIRICAL MODEL FOR THE THRESHOLD VOLTAGE OF A DOUBLE IMPLANTED MOSFET AND ITS TEMPERATURE-DEPENDENCE

[21] VLSI LIMITATIONS FROM DRAIN-INDUCED BARRIER LOWERING [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1979, 14 (02) : 383 - 391

[22] DOUBLE BORON IMPLANT SHORT-CHANNEL MOSFET [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 1977, 24 (03) : 196 - 204

[23] THRESHOLD VOLTAGE VARIATIONS WITH TEMPERATURE IN MOS TRANSISTORS [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 1971, ED18 (06) : 386 - &

[24] Ward D. E., 1982, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, VCAD-1, P163, DOI 10.1109/TCAD.1982.1270007

[25] YAU LD, 1974, SOLID STATE ELECTRON, V17, P1059, DOI 10.1016/0038-1101(74)90145-2

[21] VLSI LIMITATIONS FROM DRAIN-INDUCED BARRIER LOWERING [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1979, 14 (02) : 383 - 391

[22] DOUBLE BORON IMPLANT SHORT-CHANNEL MOSFET [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 1977, 24 (03) : 196 - 204

[23] THRESHOLD VOLTAGE VARIATIONS WITH TEMPERATURE IN MOS TRANSISTORS [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 1971, ED18 (06) : 386 - &

[24] Ward D. E., 1982, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, VCAD-1, P163, DOI 10.1109/TCAD.1982.1270007

[25] YAU LD, 1974, SOLID STATE ELECTRON, V17, P1059, DOI 10.1016/0038-1101(74)90145-2