JOSEPHSON 2-BIT FULL ADDER UTILIZING WIDE MARGIN FUNCTIONAL GATES

[1] ANACKER W, 1979, IEEE SPECTRUM MAY, P26

[2] A 4-INPUT-AND-GATE WITH 5 ASYMMETRIC INTERFEROMETERS [J]. IEEE TRANSACTIONS ON MAGNETICS, 1981, 17 (01) : 587 - 590

[3] A PARALLEL FULL ADDER CIRCUIT USING JOSEPHSON-JUNCTIONS [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1981, 16 (01) : 43 - 48

[4] JOSEPHSON TUNNELLING LOGIC ADDER [J]. IEEE TRANSACTIONS ON MAGNETICS, 1974, MA10 (03) : 864 - 867

[5] HERRELL DJ, 1978, P INT CRYO ENG C, P432

[6] SOME SYSTEM IMPLICATIONS OF A JOSEPHSON COMPUTER-TECHNOLOGY [J]. PROCEEDINGS OF THE IEEE, 1981, 69 (04) : 404 - 409

[7] Yamada H., 1979, Transactions of the Institute of Electronics and Communication Engineers of Japan, Section E (English), VE62, P749

[1] ANACKER W, 1979, IEEE SPECTRUM MAY, P26

[2] A 4-INPUT-AND-GATE WITH 5 ASYMMETRIC INTERFEROMETERS [J]. IEEE TRANSACTIONS ON MAGNETICS, 1981, 17 (01) : 587 - 590

[3] A PARALLEL FULL ADDER CIRCUIT USING JOSEPHSON-JUNCTIONS [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1981, 16 (01) : 43 - 48

[4] JOSEPHSON TUNNELLING LOGIC ADDER [J]. IEEE TRANSACTIONS ON MAGNETICS, 1974, MA10 (03) : 864 - 867

[5] HERRELL DJ, 1978, P INT CRYO ENG C, P432

[6] SOME SYSTEM IMPLICATIONS OF A JOSEPHSON COMPUTER-TECHNOLOGY [J]. PROCEEDINGS OF THE IEEE, 1981, 69 (04) : 404 - 409

[7] Yamada H., 1979, Transactions of the Institute of Electronics and Communication Engineers of Japan, Section E (English), VE62, P749