IMPROVEMENT OF THE GATE OXIDE INTEGRITY BY MODIFYING CRYSTAL PULLING AND ITS IMPACT ON DEVICE FAILURES

被引：7

作者：

WINKLER, R ^{[1
]}

SANO, M ^{[1
]}

机构：

[1] SUMITOMO SITIX CORP,CTR SILICON TECHNOL,KOUHO KU,SAGA 84905,JAPAN

来源：

JOURNAL OF THE ELECTROCHEMICAL SOCIETY | 1994年 / 141卷 / 05期

关键词：

crystal defects; crystal growth from melt; dielectric thin films integrated circuit reliability; DRAM chips; failure analysis; silicon;

D O I：

10.1149/1.2054932

中图分类号：

O646 [电化学、电解、磁化学];

学科分类号：

081704 ;

摘要：

Czochralski single-crystal wafers grown with different pulling rates using various hot zone modifications were analyzed with respect to grown-in defects and gate oxide integrity (GOI). The quality of the wafers characterized by crystal defect density as well as by GOI yield was found to be related strongly with the pulling conditions. Depending on the growth rate two concentric regions, characterized by different GOI and grown-in defect levels and separated by a ring-like area with high stacking fault density, were found on the wafers. The single-bit failure rate in some dynamic random access memory (DRAM) reliability tests turned out to correlate with GOI yield. Thus it is clearly shown that the bulk quality related with crystal pulling conditions correlates with the DRAM reliability

引用

页码：1398 / 1401

页数：4

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