OPTIMIZATION OF DEVICE AREA AND OVERALL DELAY FOR CMOS VLSI DESIGNS

被引:10
作者
LEWIS, ET [1 ]
机构
[1] TUFTS UNIV,MEDFORD,MA 02155
关键词
D O I
10.1109/PROC.1984.12916
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
引用
收藏
页码:670 / 689
页数:20
相关论文
共 20 条
[1]  
ANCEAU F, 1982, IEEE J SOLID STATE C, V17
[2]  
BORGINI F, 1981, RCA ENG, V26
[3]  
LEWIS ET, 1983, OCT ISHM PHIL
[4]  
LEWIS ET, 1982, DELETTR8003022 ERADC
[5]  
LIN HC, 1975, IEEE J SOLID-ST CIRC, VSC10, P106
[6]  
MEAD C, 1980, INTRO VLSI SYSTEMS, P12
[7]  
MEAD CA, 1982, IEEE J SOLID STATE C, V17
[8]   DELAY-TIME OPTIMIZATION FOR DRIVING AND SENSING OF SIGNALS ON HIGH-CAPACITANCE PATHS OF VLSI SYSTEMS [J].
MOHSEN, AM ;
MEAD, CA .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1979, 14 (02) :462-470
[9]   COMPUTER-AIDED-DESIGN OF VLSI CIRCUITS [J].
NEWTON, AR .
PROCEEDINGS OF THE IEEE, 1981, 69 (10) :1189-1199
[10]  
NEWTON AR, 1979, IEEE T CIRCUITS SYST, V26