SHALLOW TRENCH ISOLATION FOR ULTRA-LARGE-SCALE INTEGRATED DEVICES

被引：20

作者：

BLUMENSTOCK, K ^{[1
]}

THEISEN, J ^{[1
]}

PAN, P ^{[1
]}

DULAK, J ^{[1
]}

TICKNOR, A ^{[1
]}

SANDWICK, T ^{[1
]}

机构：

[1] IBM CORP,TECHNOL PROD,HOPEWELL JCT,NY 12533

来源：

JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B | 1994年 / 12卷 / 01期

关键词：

D O I：

10.1116/1.587107

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A new process to form shallow trench isolation for ultra-large-scale integrated devices is presented. This technique utilizes chemical mechanical polish steps to provide a virtual planar surface at the end of processing for isolation of various size, ranging from 0.5 mum to several hundred mum. Superior uniformity has been obtained on wafers of 8 in. diam processed in a productionlike environment. Good device isolation also has been found.

引用

页码：54 / 58

页数：5

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