A 68-NS 4-MBIT CMOS EPROM WITH HIGH-NOISE-IMMUNITY DESIGN

被引：5

作者：

IMAMIYA, K

MIYAMOTO, J

ATSUMI, S

OHTSUKA, N

MUROYA, Y

SAKO, T

HIGASHINO, M

IYAMA, Y

MORI, S

OHSHIMA, Y

ARAKI, H

KANEKO, Y

NARITA, K

ARAI, N

YOSHIKAWA, K

TANAKA, S

机构：

[1] TOSBAC COMP SYST INC,TOKYO,JAPAN

[2] TOSHIBA MICROELECTR CORP,KAWASAKI,JAPAN

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1990年 / 25卷 / 01期

关键词：

D O I：

10.1109/4.50287

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

— In a VLSI memory, noise generated by its own operation becomes a serious problem. The noise disturbs data sensing, especially in EPROM’s which have a single-ended sensing scheme. To develop highdensity and high-speed EPROM’s, it is inevitably necessary to solve the noise problems. Incorrect EPROM functions due to the noise are discussed in this paper. High-noise-immunity circuit techniques are proposed for stable data sensing and high-speed access time. These are divided bit-line layout, reference line with dummy bit lines, and CE transition detector. Using these circuit techniques and 0.8-µm n-well CMOS technology, a 512KÐ¥ 8-bit CMOS EPROM was developed. A 68-ns access time was achieved. The die size is 5.62 mm X 15.30 mm and it is assembled in a 600-mil cerdip package. © 1990 IEEE

引用

页码：72 / 78

页数：7

共 7 条

[1]

ALI S, 1989, MAY S VLSI CIRC, P35

[2]

CANEPA G, 1988, FEB ISSCC, P120

[3]

KAMAYA M, 1988, SEP ESSCIRC, P23

[4]

MORI S, 1987, IEDM, P556

[5]

Mori S, 1985, VLSI S, P16

[6] A 4-MBIT CMOS EPROM [J].

OHTSUKA, N ;

TANAKA, S ;

MIYAMOTO, JI ;

SAITO, S ;

ATSUMI, S ;

IMAMIYA, KI ;

YOSHIKAWA, K ;

MATSUKAWA, N ;

MORI, S ;

ARAI, N ;

SHINAGAWA, T ;

KANEKO, Y ;

MATSUNAGA, JI ;

IIZUKA, T .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1987, 22 (05) :669-675

[7]

Sato M., 1985, 1985 International Symposium on Circuits and Systems. Proceedings (Cat. No.85CH2114-7), P25

← 1 →