ANALYSIS OF HIGHLY DOPED COLLECTOR TRANSISTORS BY USING 2-DIMENSIONAL PROCESS DEVICE SIMULATION AND ITS APPLICATION OF ECL CIRCUITS

We report the results of investigation of device parameters and collector-to-emitter breakdown voltages of double polysilicon self-aligned transistors with highly doped collectors using a two-dimensional process/device simulation system. Favorable phosphorus-ion implanting condition for a highly doped pedestal collector has been found to achieve high enough cutoff frequency as well as low enough ac base resistance and small base-collector capacitance keeping the minimum BV(CEO) of 3 V. We also report ECL circuit performance improvements by experiments to realize a minimum ECL gate delay time of 26.3 ps/gate at a switching current of 1.64 mA as a result of process optimization. Moreover, a 1/8 static frequency divider using T-F/F has been observed to operate up to a maximum frequency of 15.8 GHz.