A DESIGN AND PACKAGING TECHNIQUE FOR A HIGH-GAIN, GIGAHERTZ-BAND SINGLE-CHIP AMPLIFIER

被引：28

作者：

AKAZAWA, Y

ISHIHARA, N

WAKIMOTO, T

KAWARADA, K

KONAKA, S

机构：

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1986年 / 21卷 / 03期

关键词：

D O I：

10.1109/JSSC.1986.1052544

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

引用

页码：417 / 423

页数：7

共 10 条

[1]

AKAZAWA Y, 1984, 16TH P 1984 INT C SO, P213

[2]

AKAZAWA Y, 1985, SEP ESSCIRC, P312

[3]

CARSON RS, 1975, HIGH FREQUENCY AMPLI

[4]

COOKE MP, 1985, SEP ESSCIRC, P302

[5]

KONAKA S, 1984, 16TH P C SOL STAT DE, P209

[6]

NAKAGAWA K, 1984, MAY ICC 84, P771

[7] BIPOLAR MONOLITHIC AMPLIFIERS FOR A GIGABIT OPTICAL REPEATER [J].

OHARA, M ;

AKAZAWA, Y ;

ISHIHARA, N ;

KONAKA, S .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1984, 19 (04) :491-497

[8]

OHARA M, 1985, IEEE J SOLID STATE C, V20

[9] GIGABIT LOGIC BIPOLAR TECHNOLOGY - ADVANCED SUPER SELF-ALIGNED PROCESS TECHNOLOGY [J].

SAKAI, T ;

KONAKA, S ;

KOBAYASHI, Y ;

SUZUKI, M ;

KAWAI, Y .

ELECTRONICS LETTERS, 1983, 19 (08) :283-284

[10]

STRID EW, 1982, IEEE T ELECTRON DEVI, V29

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