IMPLEMENTATION AND PERFORMANCE OF AN ANALOG NONVOLATILE NEURAL-NETWORK

An integrated circuit implementation of a fully parallel analog artificial neural network is presented. We include details of the architecture, some of the important design considerations, a description of the circuits and finally actual performance data. The electrically trainable artificial neural network (ETANN) chip incorporates 64 analog neurons and 10,240 analog synapses and utilizes a 1-mum CMOS NVM process. The network calculates the dot product between a 64-element analog input vector and a 64 x 64 nonvolatile (EEPROM based) analog synaptic weight array. These calculations occur at a rate in excess of 1.3 billion interconnections per second. All elements of the computation are stored and calculated in the analog domain and strictly in parallel. A 2:1 input and neuron multiplex mode permits rates in excess of 2 billion interconnections per second and a single-chip effective network size of 64 inputs by 128 outputs. The ETANN incorporates differential signal techniques throughout for improved noise rejection. Current summing is employed for the sum of products calculations. The chip integrates approximately 400 op amps, including variable gain stages of from 20 to 54 dB. Inevitable component to component variations due to the use of minimum dimension elements are found not to be significant for operation in an adaptive environment.