AVPGEN - A TEST GENERATOR FOR ARCHITECTURE VERIFICATION

被引：47

作者：

CHANDRA, A

IYENGAR, V

JAMESON, D

JAWALEKAR, R

NAIR, I

ROSEN, B

MULLEN, M

YOON, J

ARMONI, R

GEIST, D

WOLFSTHAL, Y

机构：

[1] IBM CORP,DIV RES,THOMAS J WATSON RES CTR,YORKTOWN HTS,NY 10598

[2] IBM CORP,DIV SYST TECHNOL & ARCHITECTURE,POUGHKEEPSIE,NY 12602

[3] IBM CORP,SCI & TECHNOL,HAIFA RES LAB,HAIFA,ISRAEL

来源：

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | 1995年 / 3卷 / 02期

关键词：

D O I：

10.1109/92.386220

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper describes a system (AVPGEN) for generating tests (called architecture verification programs or AVP's) to check the conformance of processor designs to the specified architecture. To generate effective tests, AVPGEN uses novel concepts like symbolic execution and constraint solving, along with various biasing techniques, Unlike many earlier systems that make biased random choices, AVPGEN often chooses intermediate or final values and then solves for initial values that can lead to the desired values. A language called SIGL (symbolic instruction graph language) is provided in AVPGEN for the user to specify templates with symbolic constraints. The combination of user-specified constraints and the biasing functions is used to focus the tests on conditions that are interesting in that they are likely to activate various kinds of bugs. The system has been used successfully to debug many S/390 processors and is an integral part of the design process for these processors.

引用

页码：188 / 200

页数：13

共 16 条

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