MODEL FOR PROGRAMMING WINDOW DEGRADATION IN FLOTOX EEPROM CELLS

被引：30

作者：

PAPADAS, C ^{[1
]}

GHIBAUDO, G ^{[1
]}

PANANAKAKIS, G ^{[1
]}

RIVA, C ^{[1
]}

GHEZZI, P ^{[1
]}

机构：

[1] SGS THOMSON MICROELECTR,CENT RES & DEV,I-20041 AGRATE BRIANZA,ITALY

来源：

IEEE ELECTRON DEVICE LETTERS | 1992年 / 13卷 / 02期

关键词：

Data Storage; Digital;

D O I：

10.1109/55.144968

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A theoretical model that explains the programming window degradation and the corresponding high- and low-state threshold voltage shifts as a function of the number of WRITE/ERASE operations in FLOTOX EEPROM cells is proposed. The collapse of the programming window is quantitatively related to the oxide charge buildup in the FLOTOX tunnel region as the cycling of the memory cell is increased. The simplicity of the model enables a direct application at CAD level to be foreseen.

引用

页码：89 / 91

页数：3

共 8 条

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