DEVELOPMENT OF A CMOS TIME MEMORY CELL VLSI AND A CAMAC MODULE WITH 0.5 NS RESOLUTION

被引:9
作者
ARAI, Y [1 ]
IKENO, M [1 ]
MATSUMURA, T [1 ]
机构
[1] NIPPON TELEGRAPH & TEL PUBL CORP, LSI LABS, ATSUGI, KANAGAWA 24301, JAPAN
关键词
D O I
10.1109/23.159707
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A CMOS time-to-digital converter chip, the Time Cell (TMC), for high-rate wire chamber application has been developed. The chip has a timing resolution of 0.52 ns, dissipates only 7 mW/channel, and contains 4 channels in a chip. Each channel has 1024 memory locations which art as a buffer 1 mus deep. The chip was fabricated in a 0.8 mum CMOS process and is 5.0 mm by 5.6 mm. Using the TMC chip, a CAMAC module with 32 input channels was developed. This module is designed to operate in both "Common Start" and "Common Stop" modes. The circuit of the module and test results are described.
引用
收藏
页码:784 / 788
页数:5
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