INTEGRATED MOS 4-QUADRANT ANALOG MULTIPLIER USING SWITCHED CAPACITOR TECHNOLOGY FOR ANALOG SIGNAL PROCESSOR ICS

被引:11
作者
ENOMOTO, T
YASUMOTO, MA
机构
[1] NEC, Kawasaki, Jpn, NEC, Kawasaki, Jpn
关键词
D O I
10.1109/JSSC.1985.1052399
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
INTEGRATED CIRCUITS, LINEAR
引用
收藏
页码:852 / 859
页数:8
相关论文
共 7 条
[1]   MONOLITHIC ANALOG ADAPTIVE EQUALIZER INTEGRATED-CIRCUIT FOR WIDEBAND DIGITAL-COMMUNICATION NETWORKS [J].
ENOMOTO, T ;
YASUMOTO, MA ;
ISHIHARA, T ;
WATANABE, K .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1982, 17 (06) :1045-1054
[2]   DESIGN, FABRICATION, AND PERFORMANCE OF SCALED ANALOG ICS [J].
ENOMOTO, T ;
ISHIHARA, T ;
YASUMOTO, MA ;
AIZAWA, T .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1983, 18 (04) :395-402
[3]  
Harp J. G., 1975, P C APPLICATION CCDS, P229
[4]   HIGH-SPEED NMOS OPERATIONAL-AMPLIFIER FABRICATED USING VLSI TECHNOLOGY [J].
ISHIHARA, T ;
ENOMOTO, T ;
YASUMOTO, M ;
AIZAWA, T .
ELECTRONICS LETTERS, 1982, 18 (04) :159-161
[5]  
MACK IA, 1981, 1981 P CUST INT CIRC, P128
[6]   INTEGRATED MOS 4-QUADRANT ANALOG MULTIPLIER USING SWITCHED-CAPACITOR TECHNIQUE [J].
YASUMOTO, M ;
ENOMOTO, T .
ELECTRONICS LETTERS, 1982, 18 (18) :769-771
[7]  
Yasumoto M., 1984, IEEE Journal on Selected Areas in Communications, VSAC-2, P324, DOI 10.1109/JSAC.1984.1146058