HIGH-FREQUENCY WIDE-RANGE CMOS ANALOG MULTIPLIER

被引:16
作者
SAKURAI, S
ISMAIL, M
机构
[1] The Solid-State Microelectronics Laboratory, Department of Electrical Engineering, The Ohio-State University, Columbus, OH 43210-1272
关键词
INTEGRATED CIRCUITS; SIGNAL PROCESSING; MULTIPLIERS; CIRCUIT DESIGN;
D O I
10.1049/el:19921431
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A new CMOS analogue cell which can be used to implement a four-quadrant multiplier circuit is introduced. Simulation results of the circuit using the MOSIS 2 mum process parameters are given. The circuit has an input range of +/- 4 V and linearity error less than 1% for inputs up to +/- 3 V. The magnitude and phase response are very flat; even at 30 MHz the change in the magnitude is less than 0.086 dB (1%) and the phase shift is less than 5-degrees.
引用
收藏
页码:2228 / 2229
页数:2
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