A 10-B 50-MHZ CMOS D/A CONVERTER WITH 75-OMEGA BUFFER

A 10-b 50-MHz digital-to-analog (D/A) converter is presented which is based on a dual-ladder resistor string. This approach allows the linearity requirements to be met without the need for selection or trimming. The D/A decoding scheme reduces the glitch energy, and signal-dependent switch signals reduce high-frequency distortion. The output buffer allows driving 1 Vpp to 75 O. The chip consumes 65 mW at maximum clock frequency and a full-swing output signal. The device is processed in a standard 1.6-pm CMOS process with a single 5-V supply voltage. © 1990 IEEE