3V MOS CURRENT CONVEYOR CELL FOR VLSI TECHNOLOGY

被引：44

作者：

CHENG, MCH

TOUMAZOU, C

机构：

[1] Department of Electrical and Electronic Engineering, Imperial College of Science, Technology and Medicine, London SW7 2BT, Exhibition Road

来源：

ELECTRONICS LETTERS | 1993年 / 29卷 / 03期

关键词：

CIRCUIT THEORY AND DESIGN; INTEGRATED CIRCUITS; CURRENT CONVEYORS;

D O I：

10.1049/el:19930216

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

An MOS current conveyor design suitable for VLSI implementation is described. It uses a new circuit architecture which allows for low supply voltage operation at 3 V enhancing its application versatility as a standard cell in VLSI analogue IC design as well as in mixed-mode IC design.

引用

页码：317 / 318

页数：2