THE TIME SLICE SYSTEM

We have designed a fast readout system for silicon microstrip detectors which could be used at HERA, LHC and SSC. The system consists of an analog amplifier-comparator chip (AACC) and a digital time slice chip (DTSC). The analog chip is designed in dielectric isolated bipolar technology for low noise and potential radiation hardness. The DTSC is built in CMOS for low power use and high circuit density. The main implementation aims are low power consumption and compactness. The architectural goal is automatic data reduction, and ease of external interface. The pipelining of event information is done digitally in the DTSC. It has a 64 word deep level 1 buffer acting as a FIFO and a 16 word deep level 2 buffer acting as a dequeue. The DTSC also includes an asynchronous bus interface. We are first building a scaled up (100 μm instead of 25 μm pitch) and slower (10 MHz instead of 60 MHz) version in 2 μm CMOS and plan to test the principle of operation of this system in the Leading Proton Spectrometer (LPS) of the ZEUS detector at HERA. Another very important development will be tested there: the radiation hardening of the chips. We have started a collaboration with a rad-hard foundry and with Los Alamos National Laboratories to test and evaluate rad-hard processes and the final rad-hard product. Initial data are very promising because radiation resistance of up to many Mrad have been achieved. © 1990.