OPTIMAL SYNTHESIS OF HIGH-PERFORMANCE ARCHITECTURES

An integer programming (IP) model, which simultaneously schedules and allocates functional units, registers, and buses, is presented for synthesizing cost-contrained globally optimal architectures. This research is important for industry by providing optimal schedules that minimize interconnect costs and interface to analog and asynchronous processes, since these are seen as key to synthesizing high-performance architectures. A mathematical IP model of the architectural synthesis problem is formulated. A subset of the constraints is transformed into the node-packing problem and integral facets are extracted and generalized. Other constraints are tightened or mapped into the knapsack problem and facets are extracted and generalized. Area-delay cost functions are minimized using branch and bound on the resulting IP model. Globally optimal architectures are synthesized in faster CPU times than previous research. This research breaks new ground by: 1) providing industry with interconnect-optimized architectures since interconnect is seen as the key to high performance; 2) synthesizing globally optimal architectures in faster execution times than current heuristic techniques; 3) supporting interfaces to asynchronous and analog interfaces; and 4) supporting piece-wise linear area-delay cost functions.