A PIPELINED 330-MHZ MULTIPLIER

An 8 multiplied by 8-bit multiplier test circuit developed in a 1- mu m NMOS technology is described. To achieve a high throughput rate, extensive pipelining is used in a semisystolic fashion. It is shown that this saves area and allows for shorter cycle times compared to a pure systolic array. Problems with widely distributed lines (broadcasting) are avoided by a novel carry-save-adder cell. The data inputs and outputs are ECL-compatible. The circuit contains 5480 MOSFETs in an active area of 0. 6 mm**2 . Effective channel lengths of 0. 9- and 1. 1- mu m are utilized for the enhancement and depletion transistors with a gate-oxide thickness of 12. 5 nm. The power dissipation is 1. 5 W at a supply voltage of 3 V. The test chip operates up to a clock frequency of 330 MHz at room temperature and up to 600 MHz with liquid-nitrogen cooling. This demonstrates the applicability of large-scale integrated MOS circuits in a frequency range of several hundred megahertz.