A JOSEPHSON 10-B INSTRUCTION 128-WORD ROM UNIT

被引:5
作者
AOYAGI, M
NAKAGAWA, H
KUROSAWA, I
KOSAKA, S
OKADA, Y
HAMAZAKI, Y
TAKADA, S
机构
[1] ELECTROTECH LAB,DIV COMP SCI,DISTRIBUTED SYST SECT,TSUKUBA 305,JAPAN
[2] ELECTROTECH LAB,SUPERCONDUCT ELECTR SECT,TSUKUBA 305,JAPAN
关键词
D O I
10.1109/4.58289
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A Josephson instruction read-only memory unit (IROU) has been demonstrated. The IROU, which is composed of a 10-b × 128-word ROM plane, a 6-64 decoder, two multiplexers, and several buffers, has a function of storing a program for the Josephson computer ETL-JCl. The ROM plane has been designed using two-junction dc-SQUID type ROM cells, in which the zero ROM cell has no junction and no superconducting loop and the one ROM cell has a damping resistor. The peripheral circuits have been designed using a 4JL family of or, AND, INVERT, and AMP gates. The IROU chip was fabricated using a Nb/AIOx./Nb Josephson tunnel junction IC technology with a 3-µm design rule. There were 1280 ROM cells and 789 4JL gates integrated on the 5-mm×3.45-mm chip. All 128 words of the ROM plane could be read with the total power dissipation of 1.63 mW. The minimum total access time was measured to be 390 ps. © 1990 IEEE
引用
收藏
页码:971 / 978
页数:8
相关论文
共 14 条
  • [1] SUB-MICRON NBN JOSEPHSON TUNNEL-JUNCTIONS FOR DIGITAL APPLICATIONS
    AOYAGI, M
    SHOJI, A
    KOSAKA, S
    NAKAGAWA, H
    TAKADA, S
    [J]. IEEE TRANSACTIONS ON MAGNETICS, 1989, 25 (02) : 1223 - 1226
  • [2] 32K READ-ONLY-MEMORY CHIP DESIGN IN JOSEPHSON-TECHNOLOGY - A FEASIBILITY STUDY
    BEHA, H
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1986, 21 (02) : 353 - 361
  • [3] HATANO Y, 1987, 1987 INT SUP EL C, V51, P239
  • [4] JOSEPHSON ADDRESS CONTROL UNIT-IC FOR A 4-BIT MICROCOMPUTER PROTOTYPE
    KOSAKA, S
    NAKAGAWA, H
    KAWAMURA, H
    OKADA, Y
    HAMAZAKI, Y
    AOYAGI, M
    KUROSAWA, I
    SHOJI, A
    TAKADA, S
    [J]. IEEE TRANSACTIONS ON MAGNETICS, 1989, 25 (02) : 789 - 794
  • [5] 3.0 PS SWITCHING OPERATION IN ALL-NB JOSEPHSON LOGIC GATES
    KURODA, K
    NAKANO, J
    YUDA, M
    UEKI, M
    [J]. ELECTRONICS LETTERS, 1987, 23 (04) : 163 - 165
  • [6] KUROSAWA I, 1989, 1989 INT SUP EL C PL, V31, P302
  • [7] KUROSAWA I, 1984, MAR IECE NAT CONV 2, P117
  • [8] A JOSEPHSON 4-BIT RALU FOR A PROTOTYPE COMPUTER
    NAKAGAWA, H
    KOSAKA, S
    KAWAMURA, H
    KUROSAWA, I
    AOYAGI, M
    HAMAZAKI, Y
    OKADA, Y
    TAKADA, S
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1989, 24 (04) : 1076 - 1084
  • [9] NB/AL-OXIDE/NB TUNNEL-JUNCTIONS FOR JOSEPHSON INTEGRATED-CIRCUITS
    NAKAGAWA, H
    NAKAYA, K
    KUROSAWA, I
    TAKADA, S
    HAYAKAWA, H
    [J]. JAPANESE JOURNAL OF APPLIED PHYSICS PART 2-LETTERS, 1986, 25 (01): : L70 - L72
  • [10] NAKAGAWA H, 1990, IECE SCE8959 TECHN R, P43