A 9.5-GB/S SI-BIPOLAR ECL ARRAY

This paper describes a 9.5-Gb/s Si-bipolar ECL array that has a gate delay of 35 ps, a rise time of 45 ps, and a fall time of 40 ps. We used four techniques to develop this array. We optimized the ECL circuit design and the chip layout. We used a Si-bipolar process with 0.3-mum emitter width and packaging capable of accepting 10-GHz signals. We used our ECL array in three key circuits of an optical communication system: a decision circuit, a 4 : 1 multiplexer, and a 1 : 4 demultiplexer. We confirmed operation of the decision circuit at 9.5 Gb/s, of the 4 : 1 multiplexer at 6.7 Gb/s, and of the 1 : 4 demultiplexer at 6.7 Gb/s.