A MONOLITHIC DIGITAL CHIRP SYNTHESIZER CHIP WITH I-CHANNEL AND Q-CHANNEL

A monolithic digital chirp synthesizer (DCS) chip has been developed using GaAs/AlGaAs HI2L technology. The 6500-HBT-gate DCS chip is capable of producing linear frequency-modulated (chirp) waveforms or single-frequency waveforms. The major components of the DCS are two 28-b pipelined accumulators, a 1.8-kb sine ROM, a 1.8-kb cosine ROM, and two 8-b digital-to-analog converters (DAC's). The total chip area is 4.877 mm x 6.172 mm using a minimum feature size of 1.5 mum. All components of the DCS are fully functional and the device has been clocked to 450 MHz with a power dissipation of 18 W.