DRAM PLATE ELECTRODE BIAS OPTIMIZATION FOR REDUCING LEAKAGE CURRENT IN UV-O-3 AND O-2 ANNEALED CVD DEPOSITED TA2O5 DIELECTRIC FILMS

A new plate biasing scheme is described which allowed the use of 65% higher supply voltage without increasing the leakage current for the UV-O-3 and O-2 annealed chemical-vapor-deposited tantalum pentaoxide dielectric film capacitors in stacked DRAM cells, Dielectric leakage was reduced by biasing the capacitor plate electrode to a voltage Lower than the conventionally used value of V-cc/2. Ta2O5 films with 3.9 nm effective gate oxide, 8.5 fF/mu m(2) capacitance and <0.3 mu A/cm(2) leakage at 100 degrees C and 3.3 V supply are demonstrated.