IMPACT OF THE VERTICAL SOI DELTA STRUCTURE ON PLANAR DEVICE TECHNOLOGY

被引:103
作者
HISAMOTO, D
KAGA, T
TAKEDA, E
机构
[1] Central Research Laboratory, Hitachi Ltd., Ko-, kubunji, Tokyo
关键词
D O I
10.1109/16.81634
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A fully depleted lean channel transistor (DELTA) with its gate incorporated into a new vertical ultra-thin SOI structure is presented. In the deep-submicrometer region, selective oxidation produces and isolates an ultra-thin SOI MOSFET that has high crystalline quality, as good as that of conventional bulk single-crystal devices. Experiments and three-dimensional simulations have shown that this new gate structure has effective channel control, and that the vertical ultra-thin SOI structure provides superior device characteristics: reduction in short-channel effects, minimized subthreshold swing, and high transconductance.
引用
收藏
页码:1419 / 1424
页数:6
相关论文
共 15 条
[1]   FORMATION OF SUB-MICRON SILICON-ON-INSULATOR STRUCTURES BY LATERAL OXIDATION OF SUBSTRATE-SILICON ISLANDS [J].
ARNEY, SC ;
MACDONALD, NC .
JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B, 1988, 6 (01) :341-345
[2]   REDUCTION OF KINK EFFECT IN THIN-FILM SOI MOSFETS [J].
COLINGE, JP .
IEEE ELECTRON DEVICE LETTERS, 1988, 9 (02) :97-99
[3]   SUBTHRESHOLD SLOPE OF THIN-FILM SOI MOSFETS [J].
COLINGE, JP .
IEEE ELECTRON DEVICE LETTERS, 1986, 7 (04) :244-246
[4]  
HIEDA K, 1987, DEC IEDM, P736
[5]  
HISAMOTO D, 1989, DEC IEDM, P833
[6]  
Hu C., 1983, International Electron Devices Meeting 1983. Technical Digest, P176
[7]   POWER REDUCTION TECHNIQUES IN MEGABIT DRAMS [J].
KIMURA, K ;
ITOH, K ;
HORI, R ;
ETOH, J ;
KAWAJIRI, Y ;
KAWAMOTO, H ;
SATO, K ;
MATSUMOTO, T .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1986, 21 (03) :381-389
[8]  
KUBOTA M, 1986, DEC IEDM, P814
[9]  
RICHARDSON WF, 1985, DEC INT EL DEV M, P714
[10]  
SAIHALASZ GA, 1987, DEC IEDM, P397