Recent advances in ferroelectric thin film technology have generated significant interest for use as capacitor dielectrics in semiconductor memories [1-3]. Ferroelectric non-volatile memories (NVRAMs) have several unique features which set them apart from floating-gate non-volatile memories, including high-speed write operation (intrinsic switching times below several nanoseconds [4]), high write endurance (>10(13) read/write cycles [5]) and low operating voltages (as low as 1.5 V [6]). These characteristics make ferroelectric NVRAMS excellent candidates for the non-volatile memory in portable electronic products such as RF tags, smart cards and pagers. This paper describes the operation of a ferroelectric NVRAM cell and the scaling methodology, reviews the device physics and reliability mechanisms and summarizes the challenges posed by the integration of ferroelectric capacitors with CMOS technology. The high dielectric constant (epsilon(r) similar to 300-1000) of the same class of materials used for ferroelectric NVRAMs can be exploited for high-density DRAMS. Capacitors fabricated with these materials have been shown to meet the charge storage specifications of gigabit-scale DRAMS (equivalent SiO2 thickness as low as 2.3 A [7]) without the extremely severe geometries and exceedingly complex processes required with conventional trench and stacked SiO2/Si3N4 or Ta2O5 capacitor cell technologies. Recent progress in this area is summarized.