TESTING OF A NORA CMOS SERIAL PARALLEL MULTIPLIER

被引:2
作者
BAYOUMI, MA
NAM, L
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D O I
10.1109/4.18615
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
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页码:494 / 503
页数:10
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共 26 条
[1]   MODULAR, HIGH-SPEED SERIAL PIPELINE MULTIPLIER FOR DIGITAL SIGNAL-PROCESSING [J].
BALDWIN, GL ;
MORRIS, BL ;
FRASER, DB ;
TRETOLA, AR .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1978, 13 (03) :400-408
[2]  
BASCHIERA D, 1984, VLSI DESIGN, V10, P58
[3]  
BASCHIERA D, 1986, P IEEE INT C COMPUTE
[4]  
BAYOUMI MA, 1986, 29TH P MIDW S CIRC S
[5]  
BURIC MR, 1981, JAN P CALTECH C VLSI
[6]  
CHANDRAMOULI R, 1983, 13TH P FAULT TOL COM
[7]  
CHIANG KW, 1983, 20TH P DES AUT C MIA
[8]  
CHU Y, 1962, DIGITAL COMPUTER DES
[9]  
Davis T. A., 1985, Proceedings of IEEE International Conference on Computer Design: VLSI in Computers. ICCD '85 (Cat. No.85CH2223-6), P430
[10]   TEST ROUTINES BASED ON SYMBOLIC LOGICAL STATEMENTS [J].
ELDRED, RD .
JOURNAL OF THE ACM, 1959, 6 (01) :33-36