DELAY MODELS FOR CMOS, BICMOS AND BINMOS CIRCUITS AND THEIR APPLICATIONS FOR TIMING SIMULATIONS

In this paper, we report on delay models for CMOS, BiCMOS, and BiNMOS inverters. A two-step iterative approach has been adopted to account for the slope of the input waveforms. The Alpha-Power Law model equations have been used for the short-channel MOSFET's. The effects of high collector current on the base transit time and the current gain are also included in the models of the bipolar transistors. The developed delay models are incorporated in a timing simulator to estimate the propagation delay of chains with mixed CMOS/BiCMOS/BiNMOS gates. The estimates of the simulator deviate from those of HSPICE by less than 10%, while it is faster than HSPICE by two orders of magnitudes. Hence, it can be used for identifying critical paths in VLSI systems.