REVERSE-BIAS CURRENT REDUCTION IN LOW-TEMPERATURE-ANNEALED SILICON-PN JUNCTIONS BY ULTRACLEAN ION-IMPLANTATION TECHNOLOGY

Reduction in the reverse-bias current in low-temperature-annealed silicon pn junctions has been studied. It has been shown that the transition region existing underneath the ion-implantation-generated amorphous layer and the contamination incorporated into this region play a decisive role in determining the reverse current level. In order to minimize the contamination involvement into the transition region, ultraclean ion-implantation technology has been developed. Ion implantation was carried out under a UHV (5×10 -10 Torr) condition in order to minimize the recoil implantation of adsorbed contamination at the surface. The contamination due to the high-energy ion-beam sputtering of component parts in the ion implanter has also been suppressed. As a result, a low reverse-bias current level of about 1.2×10-7 A/cm2 has been obtained for arsenic-implanted n+p junctions annealed at 550 °C, which is more than two orders of magnitude smaller than that previously reported. The stress compensation technology employing combined implantation of phosphorus and arsenic has also been shown to be very effective in reducing the lattice strain and in suppressing the damage generation.