THICKNESS LIMITATIONS OF SIO2 GATE DIELECTRICS FOR MOS ULSI

The impact of gate leakage current on MOSFET performance has been examined and limits on gate oxide thickness for static and dynamic logic have been determined. Leakage current has been found to be a greater problem for static logic than dynamic logic circuits. Gate leakage current limits the minimum oxide thickness to approximately 2 nm for static logic configurations and to approximately 3 nm in dynamic logic circuits. A poor drain design can become a limiting factor for dynamic logic circuits and raise the minimum oxide thickness required. Switching delay of static logic is relatively immune to the effects of leakage current. A MISFET with a 2.6 nm thick gate insulator of Si3N4 has been fabricated showing typical drain current characteristics, but with a large amount of gate leakage current. © 1990 IEEE