A 1-MU-M POLYSILICON SELF-ALIGNING BIPOLAR PROCESS FOR LOW-POWER HIGH-SPEED INTEGRATED-CIRCUITS

被引：11

作者：

KABZA, H

EHINGER, K

MEISTER, TF

MEUL, HW

WEGER, P

KERNER, I

MIURAMATTAUSCH, M

SCHREITER, R

HARTWIG, D

REISCH, M

OHNEMUS, M

KOPL, R

WENG, J

KLOSE, H

SCHABER, H

TREITINGER, L

机构：

来源：

IEEE ELECTRON DEVICE LETTERS | 1989年 / 10卷 / 08期

关键词：

D O I：

10.1109/55.31751

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

引用

页码：344 / 346

页数：3

共 13 条

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[2]

EHINGER K, 1988, J PHYS S, P109

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GRANT, WN .

SOLID-STATE ELECTRONICS, 1973, 16 (10) :1189-1203

[4]

KABZA H, P ESSDERC 87 BOL, P1047

[5]

Kikuchi K., 1986, International Electron Devices Meeting 1986. Technical Digest (Cat. No.86CH2381-2), P420

[6]

KONAKA S, 1984, 16TH P C SOL STAT DE, P209

[7]

LEE CA, 1969, PHYS REV, V134, pA761

[8]

SCHABER H, 1987, IEEE INT EL DEV M, P170

[9]

SCHABER H, P ESSDERC 87 BOL, P365

[10]

UENO K, 1987, IEDM TECH DIG, P371

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