ECL CMOS AND CMOS ECL INTERFACE IN 1.2-MU-M CMOS FOR 150-MHZ DIGITAL ECL DATA-TRANSMISSION SYSTEMS

This paper describes the design of a full CMOS circuit that converts digital signals from emitter-coupled logic (ECL) to CMOS and vice versa, for use in digital data transmission with clock frequencies up to 150 MHz. Extremely high performances are obtained due to a new circuit principle both in the case of the ECL-to-CMOS convertor as well in the case of the CMOS-to-ECL convertor. The paper presents a wide-band CMOS amplifier used in the ECL-to-CMOS convertor, incorporating a current injection technique to increase the bandwidth of the circuit. Further, a circuit principle is presented to realize an extremely fast CMOS-to-ECL conversion, based on a current switching technique, and charge injection to compensate the large output capacitance. Both circuits make use of replica biasing to ensure maximum switching speed in the ECL-to-CMOS convertor and correct ECL output levels in the CMOS-to-ECL convertor. An ECL-CMOS-ECL repeater has been designed in a 1.2-mu-m double-metal CMOS process. The circuit consists of four data slices, two clock slices, one frame slice, and replica circuits. It occupies 6.8 mm2 of silicon area, bonding pads included. The circuit consumes 35 mA per slice. Maximum frequency has been determined to be 175 MHz minimal. Computer simulations have shown that this limitation is caused by the inductance of the bonding wire (11 nH).