A MODULE GENERATOR FOR OPTIMIZED CMOS BUFFERS

被引:11
作者
ALKHALILI, AJ [1 ]
ZHU, Y [1 ]
ALKHALILI, D [1 ]
机构
[1] ROYAL MIL COLL CANADA,DEPT ELECT & COMP ENGN,KINGSTON K7K 5L0,ONTARIO,CANADA
关键词
circuit optimization; CMOS performance analysis; physical module generator; VLSI circuit design;
D O I
10.1109/43.62730
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
This paper gives the theory and implementation of a module generator for CMOS buffers. The generator is written in the C language and outputs optimal buffer designs in respect to a preselected objective function and layout. The user has the choice of minimizing delay, power, and area or a combination of these, plus the choice of layout configuration. The paper concentrates mainly on theoretical analysis, where variations of process, design, and layout parameters with respect to each objective function are studied in detail. © 1990 IEEE
引用
收藏
页码:1028 / 1046
页数:19
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