11.4 GBIT/S MULTIPLEXER IC EMPLOYING SUB-MICRON SI BIPOLAR TECHNOLOGY FOR USE IN FUTURE BROAD-BAND TELECOMMUNICATIONS SYSTEMS

被引：10

作者：

BAGHERI, M

HOLDEN, WS

机构：

[1] Bellcore, United States

来源：

ELECTRONICS LETTERS | 1989年 / 25卷 / 21期

关键词：

Integrated Circuits - Multiplexing Equipment - Semiconducting Silicon;

D O I：

10.1049/el:19890949

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This letter presents an 11.4 Gbit/s, 2:1 multiplexer using a 0.6 μm wide, nonpolysilicon emitter Si bipolar technology. The chip measures 0.9 × 0.8 mm2, dissipates 350 mW with a 5 V supply and is claimed to be operated at the fastest data rate reported for a multiplexer in any IC technology.

引用

页码：1422 / 1424

页数：3

共 8 条

[1]

Ballart R., 1989, IEEE COMMUN MAG, P8

[2]

BERTHOLD JE, 1989, IN PRESS P IEEE

[3] 5-GBIT/S SI INTEGRATED REGENERATIVE DEMULTIPLEXER AND DECISION CIRCUIT [J].