ANALYSIS OF COUPLING NOISE BETWEEN ADJACENT BIT LINES IN MEGABIT DRAMS

被引：27

作者：

KONISHI, Y

KUMANOYA, M

YAMASAKI, H

DOSAKA, K

YOSHIHARA, T

机构：

来源：

关键词：

D O I：

10.1109/4.16299

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

引用

页码：35 / 42

页数：8

共 17 条

[1]

Aoki M., 1988, ISSCC DIG TECH PAPER, P250

[2] VLSI WIRING CAPACITANCE [J].

COTTRELL, PE ;

BUTURLA, EM .

[3]

FURUYAMA T, 1986, ISSCC, P272

[4]

IEDA N, 1981, T IECE JAPAN JC, V64, P867

[5]

INOUE M, 1988, ISSCC DIG TECH PAPER, P246

[6]

Konishi Y., 1986, Transactions of the Institute of Electronics and Communication Engineers of Japan, Part C, VJ69C, P1560

[7]

MANO T, 1987, ISSCC DIG TECH PAPER, P22

[8]

MASHIKO K, 1987, ISSCC DIG TECH PAPER, P12

[9]

MITSUSADA K, 1980, T IECE C, V63, P61

[10]

PARENT R, 1987, ISSCC, P14