OFFSET-COMPENSATED SWITCHED-CAPACITOR DELAY-CIRCUIT THAT IS INSENSITIVE TO STRAY CAPACITANCE AND TO CAPACITOR MISMATCH

被引：9

作者：

DABROWSKI, A ^{[1
]}

MENZI, U ^{[1
]}

MOSCHYTZ, GS ^{[1
]}

机构：

[1] SWISS FED INST TECHNOL,INST SIGNAL & INFORMAT PROC,CH-8092 ZURICH,SWITZERLAND

来源：

ELECTRONICS LETTERS | 1989年 / 25卷 / 10期

关键词：

D O I：

10.1049/el:19890423

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

引用

页码：623 / 625

页数：3

共 8 条

[1] PARASITIC-COMPENSATED SWITCHED-CAPACITOR DELAY-LINES [J].

DIAS, VF ;

FRANCA, JE .

ELECTRONICS LETTERS, 1988, 24 (07) :377-379

[2] INTEGRATED TAPPED MOS ANALOG DELAY-LINE USING SWITCHED CAPACITOR TECHNIQUE [J].

ENOMOTO, T ;

ISHIHARA, T ;

YASUMOTO, MA .

ELECTRONICS LETTERS, 1982, 18 (05) :193-194

[3] STRAY-FREE SWITCHED-CAPACITOR UNIT-DELAY CIRCUIT [J].

GILLINGHAM, P .

ELECTRONICS LETTERS, 1984, 20 (07) :308-310

[4] SWITCHED CAPACITOR ANALOG DELAYS COMPRISING UNITY GAIN BUFFER [J].

MULAWKA, JJ .

ELECTRONICS LETTERS, 1981, 17 (07) :276-277

[5] SWITCHED-CAPACITOR DELAY-CIRCUIT THAT IS INSENSITIVE TO CAPACITOR MISMATCH AND STRAY CAPACITANCE [J].

NAGARAJ, K .

ELECTRONICS LETTERS, 1984, 20 (16) :663-664

[6] ALTERNATIVE APPROACH TO THE DESIGN OF SWITCHED-CAPACITOR FILTERS [J].

PAIN, BG .

ELECTRONICS LETTERS, 1979, 15 (14) :438-437

[7] SCANAL - A PROGRAM FOR THE COMPUTER-AIDED ANALYSIS OF SWITCHED-CAPACITOR NETWORKS [J].

PLODECK, R ;

BRUGGER, UW ;

VONGRUNIGEN, DC ;

MOSCHYTZ, GS .

IEE PROCEEDINGS-G CIRCUITS DEVICES AND SYSTEMS, 1981, 128 (06) :277-285

[8] STRAY-FREE SWITCHED-CAPACITOR BUILDING BLOCK THAT REALIZES DELAY, CONSTANT MULTIPLIER, OR SUMMER CIRCUIT [J].

SAID, AE .

ELECTRONICS LETTERS, 1985, 21 (04) :167-168

← 1 →