A FAST-SETTLING CMOS OP AMP FOR SC CIRCUITS WITH 90-DB DC GAIN

被引：389

作者：

BULT, K

GEELEN, GJGM

机构：

[1] Philips Research Laboratories, 5600, JA, Eindhoven

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1990年 / 25卷 / 06期

关键词：

17;

D O I：

10.1109/4.62165

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A technique is presented that combines the high-frequency behavior of a single-stage op amp with the high dc gain of a multistage design. Bode-plot measurements show a dc gain of 90 dB and a unity-gain frequency of 116 MHz (16-pF load). Settling measurements with a feedback factor of 1/3 show a fast single-pole settling behavior corresponding to a closed-loop bandwidth of 18 MHz (35-pF load) and a settling accuracy better than 0.03%. © 1990 IEEE

引用

页码：1379 / 1384

页数：6

共 17 条

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