TECHNOLOGY LIMITATIONS FOR N+/P+ POLYCIDE GATE CMOS DUE TO LATERAL DOPANT DIFFUSION IN SILICIDE POLYSILICON LAYERS

The device degradation of dual-polycide-gate N+/P+ CMOS polycide transistors due to the lateral diffusion of dopants in the silicides is studied using a coupled 2-D process and device simulator. Design rule spacings between the NMOS and the PMOS transistor are given for various NMOS:PMOS gate area ratios and thermal processing conditions. The simulations show that contrary to previous findings, micrometer and submicrometer spacings are possible for certain silicide technologies using low-temperature or short higher temperature furnace steps. Simulations show that CoSi2 and TiSi2 appear to be better candidates for submicrometer dual-gate applications compared to WSi2.