INPUT WAVE-FORM SLOPE EFFECTS IN CMOS DELAYS

被引：24

作者：

AUVERGNE, D

AZEMARD, N

DESCHACHT, D

ROBERT, M

机构：

[1] Laboratoire d’Automatique et de Microélectronique de Montpellier, Université de Montpellier II: Sciences et Techniques du Languedoc, 34095

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1990年 / 25卷 / 06期

关键词：

D O I：

10.1109/4.62196

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Slow input ramp effects in delay evaluation on CMOS structures are considered. Corrections of previously defined closed-form equations are proposed, allowing accurate evaluation of delays in a large range of configurations. © 1990 IEEE

引用

页码：1588 / 1590

页数：3

共 4 条

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AUVERGNE, D ;

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ROBERT, M .

ELECTRONICS LETTERS, 1987, 23 (14) :741-742

[2] EXPLICIT FORMULATION OF DELAYS IN CMOS DATA PATHS [J].

DESCHACHT, D ;

ROBERT, M ;

AUVERGNE, D .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1988, 23 (05) :1257-1264

[3]

Kao W. H., 1985, 22nd ACM/IEEE Design Automation Conference Proceedings 1985 (Cat. No.85CH2142-8), P781, DOI 10.1145/317825.317991

[4] A FAST-TIMING SIMULATOR FOR DIGITAL MOS CIRCUITS [J].

TSAO, D ;

CHEN, CF .

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1986, 5 (04) :536-540

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