A HALF-MICRON CMOS LOGIC GENERATION

被引:22
作者
KOBURGER, CW
CLARK, WF
ADKISSON, JW
ADLER, E
BAKEMAN, PE
BERGENDAHL, AS
BOTULA, AB
CHANG, W
DAVARI, B
GIVENS, JH
HANSEN, HH
HOLMES, SJ
HORAK, DV
LAM, CH
LASKY, JB
LUCE, SE
MANN, RW
MILES, GL
NAKOS, JS
NOWAK, EJ
SHAHIDI, G
TAUR, Y
WHITE, FR
WORDEMAN, MR
机构
[1] BAKEMAN TECHNOL,S BURLINGTON,VT 05454
[2] BERGENDAHL ENTERPRISES,UNDERHILL,VT 05489
[3] IBM CORP,DIV RES,THOMAS J WATSON RES CTR,YORKTOWN HTS,NY 10598
关键词
CMOS integrated circuits - Electric variables control - Electric wiring - Fabrication - Lithography - MOSFET devices - Random access storage - Technology;
D O I
10.1147/rd.391.0215
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
During the early 1990s, half-micron lithography was demonstrated in 16Mb DRAM fabrication. Utilization of this capability for CMOS logic devices within IBM followed with a trio of programs, each with different performance, density, feature list, and schedule. The first version melded 3.3/3.6-V 16Mb DRAM MOSFET devices with an improved version of an existing dense, planar, reliable multilevel backend-of-line (BEOL) metallization and wiring technology. Since it was built directly from existing technologies, it was released quite quickly. A 3.3-V follow-on technology was added several months later. This logic offering added a local interconnect and a faster device. A second follow-on achieved greater speed improvement, calling upon a 2.5-V power supply and very tight channel-length control to obtain performances 50% above previous-generation standards, at lower power.
引用
收藏
页码:215 / 227
页数:13
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