A COMPACT LOW-NOISE OPERATIONAL-AMPLIFIER FOR A 1.2 MU-M DIGITAL CMOS TECHNOLOGY

A compact low noise operational amplifier using lateral p-n-p bipolar transistors in the input stage has been fabricated in a standard 1.2 mu m digital n-well CMOS process, Like their n-p-n counterparts in p-well processes, these lateral p-n-p transistors exhibit low 1/f noise and good lateral beta. The fabricated op amp has an area of only 0.211 mm(2) with E(n) = 3.2 nV/root Hz, I-n = 0.73 pA/root Hz, E(n) and I-n 1/f noise corner frequencies less than 100 Hz, a -3 dB bandwidth greater than 10 MHz with a closed loop gain of 20.8 dB, a minimum PSRR (de) of 68 dB, a CMRR (de) of 100 dB, a minimum output slew rate of 39 V/mu s, and a quiescent current of 2.1 mA at supply voltages of +/-2.5 V, The operational amplifier drives a 1 k Omega resistive load to 1 V peak-to-peak at 10 MHz and has been used as a versatile building block for mixed-signal IC designs.