Josephson Junction Integrated Circuit Process with Planarized PECVD SiO2 Dielectric

被引：4

作者：

Barfknecht, A. T. ^{[1
]}

Ruby, R. C. ^{[2
]}

Ko, H. L. ^{[2
]}

Lee, G. S. ^{[2
]}

机构：

[1] Conductus Inc, 969 W Maude Ave, Sunnyvale, CA 94086 USA

[2] Hewlett Packard Labs, 3500 Deer Creek Rd, Palo Alto, CA 94303 USA

来源：

IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY | 1993年 / 3卷 / 01期

关键词：

D O I：

10.1109/77.233940

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

As part of our efforts to reach very-large-scale integration for our Nb Josephson junction circuits, we have developed a process technology that includes plasma enhanced chemical vapor deposited SiO2 for all interlayer dielectrics, as well as sacrificial resist etch-back planarization to smooth the surface topology under the trilayer.

引用

页码：2201 / 2203

页数：3

共 12 条

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