SPATIAL VERSUS TEMPORAL STABILITY ISSUES IN IMAGE-PROCESSING NEUROCHIPS

A typical image processing neuro chip consists of a regular array of very simple cell circuits. When it is implemented by a CMOS process, two stability issues naturally arise: i) Parasitic capacitors of MOS transistors induce the temporal dynamics. Since a processed image is given as the stable limit point of the temporal dynamics, a temporally unstable chip is unusable. ii) Because of the array structure, the node voltage distribution induces the spatial dynamics, and it could behave in a wild manner, e.g., oscillatory, which is highly undesirable for image processing purposes, even if the trajectory of the temporal dynamics converges to a stable limit point. The main contributions of this paper are (i) a clarification of the spatial stability issue; (ii) explicit if and only if conditions for the temporal and the spatial stability in terms of circuit parameters; (iii) a rigorous explanation of the fact that even though the spatial stability is stronger than the temporal stability, the set of parameter values for which the two stability issues disagree is of (Lebesgue) measure zero; and (iv) theoretical estimates on the processing speed.