SCALING OF DIGITAL BICMOS CIRCUITS

In this paper we present a generalized first-order scaling theory for BiCMOS digital circuit structures. The effect of horizontal, vertical, and voltage scaling on the speed performance of various BiCMOS circuits is presented. We use the generalized scaling theory for the MOSFET and the constant collector current (CIO scaling scheme for the BJT. In scaling the bipolar transistor, polysilicon emitter contact and bandgap narrowing are taken into account. A case study for scaling BiCMOS circuits operating at 5- and 3.3-V power supplies shows that scaling improved BiCMOS buffers more significantly than CMOS buffers. Moreover, the low delay-to-load sensitivity of BiCMOS is preserved with scaling. © 1990 IEEE