AN NMOS-VLSI PROCESS FOR FABRICATION OF A 32-BIT CPU CHIP

被引：11

作者：

MIKKELSON, JM

HALL, LA

MALHOTRA, AK

SECCOMBE, SD

WILSON, MS

机构：

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1981年 / 16卷 / 05期

关键词：

D O I：

10.1109/JSSC.1981.1051635

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

引用

页码：542 / 547

页数：6

共 7 条

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DOHSE, LJ ;

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LOB, CG ;

TAYLOR, GL ;

ZELLER, ER .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1981, 16 (05) :537-542

[3]

Chatterjee P. K., 1980, IEEE Electron Device Letters, VEDL-1, P220, DOI 10.1109/EDL.1980.25295

[4] DESIGN OF ION-IMPLANTED MOSFETS WITH VERY SMALL PHYSICAL DIMENSIONS [J].

DENNARD, RH ;

GAENSSLEN, FH ;

YU, HN ;

RIDEOUT, VL ;

BASSOUS, E ;

LEBLANC, AR .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1974, SC 9 (05) :256-268

[5] EVOLUTION OF DIGITAL ELECTRONICS TOWARDS VLSI [J].

KEYES, RW .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 1979, 26 (04) :271-279

[6]

MEINDL JD, 1981, 1981 IEEE INT SOL ST

[7]

Moore G. E., 1975, 1975 International Electron Devices Meeting. (Technical digest), P11

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